1. Field of the Invention
The present invention relates to a method and a system for generating coverage data for a switch frequency of HDL or VHDL signals in a cycle simulation.
2. Description of the Related Art
The verification of the logical correctness of a digital circuit design is an important process during the development of said circuit design. This said design is called device under test (DUT) in verification. The verification may be realized by a simulation process, i.e. in this case a cycle simulation process, of the DUT on a computer. Typically, the hardware designer provides a model written in a hardware description language (HDL), such as VHDL (very high speed integrated circuit hardware description language).
In the simulation of a complex hardware model a lot of signals occur. The values of all or selected signals of the simulation cycle during the whole simulation process are contained in an all-event-trace (AET). The large number of signals results in large AETs. It would be advantageous if the AETs contain only the values of the important signals. Such an AET is used for the determination of the switch frequency of the signals after the end of the simulation process.
The main function of the simulation process is the verification of the logical correctness of the hardware model and the hardware itself. In a complex hardware it is difficult to assure that all paths of the hardware are checked. It becomes more important to check certain single groups of signals during the simulation process. Such groups of signals may be input and output signals, power latch signals, spare latch signals and disable logic signals.
The U.S. Pat. No. 6,920,418 B2 describes a method for monitoring events within a simulation model. Those signals, which have to be checked, are defined by an additional VHDL code during the model is built. In the end of the simulation the signal to be checked are transmitted to a data base. This method requires that the signal must be already defined at the time of building the model. Additional signals require the building of a new model restart cycle simulation. The signals have to be inserted manually into the HDL. The use of a filter is not possible.
The U.S. Pat. No. 7,194,400 B2 describes a simulation control program, which receives a HDL model including design entities and count event registers. Each count event register is associated with a respective instance of an event. The count event registers are an integrated part of the HDL model. The HDL model describes the circuit design as well as the relevant fact of the simulation process. Thus, the simulation process is predetermined by the HDL model. When the HDL model is provided, then a variation of the signals for those you want to observe the switch frequency during the cycle simulation process is not possible.